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ML2021
Telephone Line Equalizer
Features
* * * * * * * * * * Slope, height, and bandwidth adjustable Optimized group delays (500 Hz to 6.4 kHz) On chip anti-alias filter Bypass mode Low supply current 6 mA typical from 5V supplies TTL / CMOS compatible interface Double buffered data latch Selectable master clock 1.544 or 1.536 MHz Synchronous or asynchronous data loading capability Compatible with ML2003 and ML2004 logarithmic gain/attenuator
General Description
The ML2021 is a monolithic analog line equalizer for telephone applications. The ML2021 consists of a switched capacitor filter that realizes a family of frequency response curves optimized for telephone line equalization while minimizing group delay. The ML2021 consists of a continuous anti-aliasing filter, three programmable switched capacitor equalization filters, an output smoothing filter, a 600 driver, and a digital section for the serial interface. The equalization filters adjust the slope, height, and bandwidth of the frequency response. The desired frequency response is programmed by a digital 14-bit serial input data stream.
Block Diagram
CLKSEL VCC AGND VSS
Pin Connections
ML2021 16-PIN DIP
CLKSEL 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC PDN VOUT AGND VIN VSS LATI GND
CLK
CLOCK GENERATOR
SMOOTHING FILTER
VOUT
SID NC LATO
VIN
ANTIALIAS LO PASS
MUX
SCK NC SOD
SLOPE SECTION PDN LATI 5
HEIGHT SECTION 4 14-BIT LATCH 14
BANDPASS SECTION 4
1
CLK GND
TOP VIEW
ML2021 18-PIN SOIC
SOD CLKSEL SID NC LATO SCK NC SOD CLK GND 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 VCC PDN VOUT AGND NC VIN NC VSS LATI
SID
14-BIT SHIFT REGISTER
SCK
LATO
TOP VIEW
REV. 1.1.1 3/19/01
ML2021
PRODUCT SPECIFICATION
Pin Description
Name CLKSEL SID LATO SCK SOD CLK GND LATI VSS VIN AGND VOUT PDN VCC Function Clock select input. This pin selects the frequency of the CLK input. If CLK is 1.536 MHz, set CLKSEL = 1. If CLK is 1.544 MHz, set CLKSEL = 0. Pin has an internal pullup resistor to VCC. Serial input data. Digital input that contains serial data word which controls the filter frequency response setting. Output latch clock. Digital input which loads the data word back into the shift register from the latch. Shift clock. Digital input which shifts the serial data on SID into the shift register on rising edges and out onto SOD on falling edges. Serial output data. Digital output of the shift register. Master clock input. Digital input which generates clocks for the switched capacitor filters. Frequency can be either 1.544 MHz or 1.536 MHz. Digital ground. 0 volts. All digital inputs and output are referenced to this ground. Input latch clock. Digital input which loads data from the shift register into the latch. Negative supply. -5volts 10%. Analog input. Analog ground. 0 volts. Analog input and output are referenced to this ground. Analog output. Powerdown input. When PDN = 1, device is in powerdown mode. When PND = 0, device is in normal operation. This pin has an internal pulldown resistor to GND. Positive supply. 5 volts 10%
Absolute Maximum Ratings1
Parameter Supply Voltage VCC VSS AGND with respect to GND Analog Input and Output Digital Input and Outputs Input Current Per Pin Power Dissipation Storage Temperature Range Lead Temperature (Soldering, 10 sec) -65 VSS -0.3 GND -0.3 Min. Max. +6.5 -6.5 0.5 VCC +0.3 VCC +0.3 25 750 +150 300 Units V V V V V mA mW C C
Operating Conditions
Parameter Temperature ML2021CX ML2021IX Range2 0 -40 4 -4 70 85 6 -6 C C V V Min. Max. Units
Supply Voltage VCC VSS
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REV. 1.1.1 3/19/01
PRODUCT SPECIFICATION
ML2021
Electrical Characteristics
Unless otherwise specified TA = TMIN to TMAX, VCC = 5V 10%, VSS = -5V 10%, Data Word: BP = 1, Other Bits = 0, CL = 100pF, RL = 600, dBm measurements use 600 as reference load, VIN = -7dBm, 1kHz sinusoid CLK = 1.544 MHz 300 Hz and digital time measured at 1.4 V Symbol Analog SR Response, Slope Section 4 1 kHz response
NL/L 0 0 0 0 0 1 1 1 1 1 1 S3 0 0 0 1 1 0 0 0 0 1 1 S2 0 0 1 0 1 0 0 0 1 0 1 S1 0 1 0 0 1 0 0 1 0 0 1 S0 1 0 0 0 1 0 1 0 0 0 1 1.4 0.1 2.6 0.2 4.7 0.2 7.8 0.2 11.4 0.25 0 0.1 0.4 0.1 0.9 0.2 1.8 0.2 3.7 0.2 6.6 0.25 dB dB dB dB dB dB dB dB dB dB dB
Parameter
Notes
Conditions
Min Typ.3
Max.
Units
Referenced to
0 0 0 0 0
HR
Response, Height Section
4
3250 Hz response referenced to 1 kHz response with BP = 1, other bits = 0
NL/L H3 0 0 0 0 0 0 0 0 0 0 1 1 B2 0 0 0 1 0 1 H2 0 0 0 1 0 1 B1 0 0 1 0 0 1 H1 0 0 1 0 0 1 B0 0 1 0 0 0 1 H0 0 1 0 0 0 1 H3 1 1 1 1 1 1 H2 1 1 1 1 1 1 H1 1 1 1 1 1 1 H0 1 1 1 1 1 1 16.1 2.0 14.2 1.5 12.6 1.5 9.1 1.0 3.6 0.5 1.2 0.35 0 0.15 0.5 0.2 1.1 0.2 2.3 0.2 5.7 0.3 11.1 0.3 dB dB dB dB dB dB
BR
Response, Bandwidth Section (Q)
4
NL/L 0 0 0 0 0 0
B3 0 0 0 0 1 1
PK AG AGB ICN HD
BW Peak Frequency Absolute Gain, Flat Response Absolute Gain, Bypass Mode Idle Channel Noise Harmonic Distortion
4 4 4 4 4
H3 thru H0 = 1 0.5 kHz to 4 kHz 0.3 kHz to 4 kHz, BP = 0 VIN = 0 VIN = 0, All Data Bits = 1 VIN = 5 dBm, 1 kHz Measure 2nd, 3rd, harmonic relative to fundamental VIN = -12dBm, 1 kHz C msg weighted VIN = 0, 4 kHz frequency 150 kHz 200mVp-p, 1 kHz sine, VIN = 0 on VCC on VSS
3230 3250 -0.1 +0.1 -0.1 +0.1 3 9
3270 +0.3 +0.3 8 -48
Hz dB dB dBrnc dBrnc dB
SD SFN PSRR
Signal to Distortion Signal Frequency Noise Power Supply Rejection
4 5 4
+48 -50 -40 -40
dB dBm dB dB
REV. 1.1.1 3/19/01
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ML2021
PRODUCT SPECIFICATION
Electrical Characteristics (continued) Unless otherwise specified TA = TMIN to TMAX, VCC = 5V 10%, VSS = -5V 10%, Data Word: BP = 1, Other Bits = 0, CL = 100pF, RL = 600, dBm measurements use 600 as reference load, VIN = -7dBm, 1kHz sinusoid CLK = 1.544 MHz 300 Hz and digital time measured at 1.4 V
Symbol ZIN VOS VINR VOSW VIL VIH VOL VOH ILCLK ILPDN IL ICC ISS ICCP ISSP Parameter Input Impedance, VIN Output Offset Voltage Input Voltage Range Output Voltage Swing Digital Input Low Voltage Digital Input High Voltage Digital Output Low Voltage Digital Output High Voltage Input Current, CLK SEL Input Current, PDN Input Current, All Other Inputs VCC Supply Current VSS Supply Current VCC Supply Current, Powerdown Mode VSS Supply Current, Powerdown Mode Clock Duty Cycle SCK On/Off Period SID Data Setup Time SID Data Hold Time SOD Data Delay LATI Pulse Width LATO Pulse Width LATI, LATO Setup Time LATI, LATO Hold Time SOD Parallel Load Delay Notes 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 IOL = 2mA IOH = -1mA VIN = 0 VIN = VCC VIN = 0 to VCC No output load, VIL = GND, VIH = VCC, VIN = 0 No output load, VIL = GND, VIH = VCC, VIN = 0 No output load, VIL = GND, VIH = VCC No output load, VIL = GND, VIH = VCC 40 250 50 50 0 50 50 50 50 0 125 125 4.0 5 -3 100 -100 10 10 -10 1.2 -1.2 2.0 0.4 RL = 600 VIN = 0 2.0 2.0 0.8 Conditions Min Typ.3 100 50 Max. Units k mV V V V V V V A A A mA mA mA mA
Digital and DC
AC Characteristics tDC tSCK tS tH tD tIPW tOPW tIS, tOS tIH, tOH tPLD 5 4 4 4 4 4 4 4 5 4 60 % ns ns ns ns ns ns ns ns ns
Notes 1. Absolute maximum ratings are limits beyond which the life of the integrated circuit may be impaired. All voltages unless otherwise specified are measured with respect to ground. 2. 0C to +70C and -40C to +85C operating temperature range devices are 100% tested with temperature limits guaranteed by 100% testing, sampling, or by correlation with worst-case test conditions. 3. Typicals are parametric norm at 25C. 4. Parameter guaranteed and 100% production tested. 5. Parameter guaranteed. Parameters not 100% tested are not in outgoing quality level calculation.
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REV. 1.1.1 3/19/01
PRODUCT SPECIFICATION
ML2021
tSCK SCK tS SID tD SOD tH
tSCK
SCK tIS LATI tIPW LATO tPLD SOD tOPW tIH tOS tOH
TIMING PARAMETERS ARE REFERENCED TO THE 1.4 VOLT MIDPOINT.
Figure 1. Serial Timing Diagram
1111 12 10.5 GROUP DELAY--d/df(s) 9.0 AMPLITUDE (dB) 7.5 6.0 4.5 3.0 1.5 0
0000
120 100 80 60 40 20 0 -20 -40 -60 -80 0 500 1000 1500 2000 2500 FREQUENCY (Hz) 3000 3500 4000 0 500 1000 1500 2000 2500 FREQUENCY (Hz) 3000 3500 4000 0000 0001 0010 0100 1000 1111
-1.5 -3.0
Figure 2. Typical Slope Filter Response--NL/L = 0 B3-B0, H3-H0 = 0000, S3-S0 = 0000 to 1111.
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ML2021
PRODUCT SPECIFICATION
12 1111 10.5 GROUP DELAY - d/df (s) 9.0 AMPLITUDE (dB) 7.5 6.0 4.5 3.0 1.5 0 -1.5 -3.0 0 500 1000 1500 2000 2500 3000 3500 4000 FREQUENCY (Hz) 0000
40 20 0 -20 0001 -40 -60 -80 -100 -120 -140 -160 0 500 1000 1500 2000 2500 FREQUENCY (Hz) 3000 3500 4000 1000 1111 0010 0100 0000
Figure 3. Typical Slope Filter Response--NL/L = 1 B3-B0, H3-H0 = 0000, S3-S0 = 0000 to 1111.
12 10.5 9.0 AMPLITUDE (dB) 7.5 6.0 4.5 3.0 1.5 0 -1.5 -3.0 0 500 1000 1500 2000 2500 3000 3500 4000 FREQUENCY (Hz) 0001 0000 0100 0010 1000 GROUP DELAY - d/df (s) 1111 1200 1000 1000 800 600 0100 400 200 0 -200 0 500 1000 1500 2000 2500 FREQUENCY (Hz) 0000 3000 3500 4000 0010 0001 1111
Figure 4. Typical Height Filter Response--NL/L = 0 B3-B0, S3-S0 = 0000, H3-H0 = 0000 to 1111.
12 10.5 GROUP DELAY - d/df (s) 9.0 AMPLITUDE (dB) 7.5 6.0 4.5 3.0 1.5 0 -1.5 -3.0 0 500 1000 1500 2000 2500 3000 3500 4000 FREQUENCY (Hz) -200 0 500 1000 1500 2000 2500 FREQUENCY (Hz) 3000 3500 4000 0000 1111 1200 1000 800 600 400 200 0 1000 1111 0000 0001 0010 0100
Figure 5. Typical Bandwidth Filter Response--NL/L = 0 H3-H0 = 1111; S3-S0 = 0000; B3-B0 = 0000 to 1111.
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REV. 1.1.1 3/19/01
PRODUCT SPECIFICATION
ML2021
Functional Description
The ML2021 consists of a continuous anti-alias filter, three programmable switched capacitor equalization filters, an output smoothing filter, an output driver, and a digital section for the serial interface.
There is an additional bit, NL/L, that also affects the highpass response of the slope filter. The slope response curves in Figure 2 are with NL/L = 0. These same response curves are shown in Figure 3 with NL/L = 1. Notice that the NL/L bit adds more droop in the highpass response below 2500 Hz. The family of response curves generated by the height section are shown in Figure 4. There are 4 height select bits, H3-H0. This section creates a peak in the response at 3250 Hz and this filter controls the amount of peaking. Table 2 gives typical 1 kHz gain values for all height and bandwidth settings.
Table 2. Typ. 1kHz Gain for HT and BW Settings
Relative 1kHz Gain (dB) HT Setting 0
0 1 2 3 4 5 Rel 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Anti-Alias Filter
The first section is a continuous anti-alias filter. This filter is needed to prevent aliasing of high frequency signal present on the input into the passband by the sampling action of the switched capacitor filters. This section is a continuous second order lowpass filter with a typical 3 dB frequency at 20 kHz and 30 dB of rejection at 124 kHz.
Equalization Filters
The programmable filters implement a family of frequency response curves intended to compensate for the response of telephone lines. This filter is composed of three distinct sections: slope, height, and bandwidth.
BW Setting 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
2
0 0 0 0 0 0 0 0 0 0 0 0
3
0 0 0 0 0 0 0 0 0 0
4
0 0 0 0 0 0 0 0 0 0
5
0 0 0 0 0 0 0 0
6
0 0 0 0 0 0 0 0
7
0 0 0 0 0 0 0 0
8
0 0 0 0 0 0
9 10 11 12 13 14 15
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0.1 0.1 0.1 0.1 0.1
Response of Slope, Height, and Bandwidth
The family of response curves generated by the slope section are shown in Figures 2 and 3. There are 4 slope select bits, S3-S0. These bits alter the slope of the highpass response under 1000Hz, and as a result, the absolute gain above 1000 Hz will be unique for each setting. Table 1 gives typical 1 kHz gain values for all slope settings.
Table 1. Typ. 1kHz Gain for Slope Settings
6 7 8 9 10 11 12 13 14 15
0 0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.2 0.2 0.2
0 0.1 0.1 0.1 0.1 0.1 0.2 0.2 0.3 0.3 0.4 0.1 0.1 0.1 0.1 0.2 0.2 0.3 0.3 0.4 0.5 0.6
0 0.1 0.1 0.1 0.1 0.2 0.3 0.3 0.4 0.5 0.6 0.7 0.8 0.1 0.1 0.1 0.2 0.2 0.3 0.4 0.4 0.5 0.7 0.8 0.9 1.1
0.1 0.1 0.1 0.2 0.2 0.3 0.4 0.5 0.7 0.8 1.0 1.1 1.4 1.6 0.1 0.1 0.2 0.3 0.4 0.5 0.6 0.8 0.9 1.1 1.4 1.6 1.9 2.3 0.1 0.1 0.2 0.3 0.4 0.5 0.7 0.8 1.0 1.2 1.5 1.7 2.0 2.4 0.1 0.1 0.2 0.3 0.4 0.5 0.7 0.9 1.1 1.3 1.6 1.8 2.1 2.5
Slope Bits = 0
Slope Setting 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 HT, BW Bits = 0
Rel 1kHz Gain (dB) NL/L = 1 0.0 0.4 0.9 1.4 1.8 2.3 2.8 3.4 3.7 4.2 4.6 5.0 5.4 5.8 6.2 6.6 NL/L = 0 REL 1.4 2.6 3.7 4.7 5.5 6.3 7.2 7.8 8.4 9.0 9.5 10.0 10.5 11.0 11.4 The family of response curves generated by the bandwidth section is shown in Figure 5. There are 4 bandwidth select bits, B3-B0. This section causes the response of the 3250 Hz peak to be widened, and as a result, this filter controls the bandwidth of the 3250 Hz peaked region.
Transfer Function
The transfer function for the ML2021 is shown below. This transfer function is valid for magnitude response only. The actual magnitude response from an individual device may deviate from the computed response from the transfer function by typically 0-0.2 dB.
2 c (s + b ) [ s + h ( o Q )s + o ] [ sin ( f fc ) ] H ( s ) = -------------------- x --------------------------------------------------------- x ------------------------------( f fc ) b ( s + c ) [ s 2+ ( Q )s + 2 ] o o 2
s o fc b,c Q h
= = = : : :
j x 256000 x tan (f/128000) 20463.77 128000 See Table 3. (slope) See Table 4. (bandwidth) See Table 5. (height)
REV. 1.1.1 3/19/01
7
ML2021
PRODUCT SPECIFICATION
Table 3. Slope Response Factors (b,c)
Group Delay
The difference between the ML2020 and ML2021 is the elimination of a 60 Hz highpass filter in order to eliminate positive group delay at low frequency. The group delay through the ML2021 can be minimized such that less than 50s of group delay can be achieved in both unloaded and cable loaded conditions relative to 1804 Hz in the frequency range of 504 to 3004Hz. Minimum group delays are dependant upon using the proper setting for slope, height, and bandwidth for a give equalization requirement.
S3-0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 S3-0 XXXX
b NL/L = 0 2.371759E +03 1.985920E + 03 1.701779E + 03 1.493571E + 03 1.326721E + 03 1.196668E + 03 1.087277E + 03 9.983588E + 02 9.179889E + 02 8.537864E + 02 7.966049E + 02 7.478074E + 02 7.035099E + 02 6.651771E + 02 6.299477E + 02 5.990361E + 02 c NL/L = 0 2.371759E + 03
b NL/L = 1 1.116280E + 04 9.345141E + 03 8.007156E + 03 7.026999E + 03 6.241681E + 03 5.629636E + 03 5.114881E + 03 4.696487E + 03 4.318339E + 03 4.016273E + 03 3.747249E + 03 3.517676E + 03 3.309279E + 03 3.128945E + 03 2.963214E + 03 2.817797E + 03 c NL/L = 1 1.116280E + 04
Smoothing Filter
The equalizer filters are followed by a continuous second order smoothing filter that removes the high frequency sample information generated by the action of the switched capacitor filters. This filter provides a continuous analog signal at the output, VOUT.
Output Buffer
The final stage in the ML2021 is the output buffer. This amplifier has internal gain of 1 and is capable of driving 600, 100pF loads. Thus, it is suitable for driving telephone hybrids directly without any external amplifier.
Table 4. Slope Response factors (b,c)
B3-0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Q 17.444906 15.386148 13.652451 11.593677 9.859960 8.017864 6.392453 5.092080 3.900003 3.141338 2.599369 2.165724 1.731965 1.406509 1.352248 1.297981
Bypass Mode
The filter sections can be bypassed by setting the bypass data bit, BP, to 0. Since the switched capacitor filters are bypassed in this mode, frequency response effects of the switched capacitor filters are eliminated. Thus, this mode offers very flat response and low noise over the 300-4000 Hz frequency range.
Filter Clock
The master clock, CLK, is used to generate the internal clocks for the switched capacitor filters. The frequency of CLK can be either 1.544 MHz or 1.536 MHz. However, the internal clock frequency must be kept at 1.536 MHz to guarantee accurate frequency response. The CLKSEL pin enables a bit swallower circuit to keep the internal clock frequency set to 1.536 MHz. When 1.544 MHz clock is used, CLKSEL should be set to logic level 0, and one bit out of every 193 bits is removed (swallowed) to reduce the internal frequency to 1.536 MHz. When 1.536 MHz clock is used, CLKSEL should be set to logic level 1, and the internal clock rate is the same as the external clock rate.
Table 5. Height Response Factors (h)
Code 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
h 1.000000 1.071519 1.148154 1.230269 1.318257 1.445438 1.603245 1.757924 1.949845 2.137962 2.317395 2.540973 2.786121 3.019951 3.311311 3.672823
Serial Interface
The architecture of the digital section is shown in the preceding block diagram. A timing diagram for the serial interface is shown in Figure 6. The serial input data, SID, is loaded into a shift register on rising edges of the shift clock, SCK. The data word is parallel loaded into a latch when the input latch signal, LATI, is
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REV. 1.1.1 3/19/01
PRODUCT SPECIFICATION
ML2021
high. The LATI pulse must occur when SCK is low. A new data word can be loaded into the shift register without disturbing the existing data word in the latch. The parallel outputs of the latch control the filter response curves. The order of the data word bits in the latch is shown in Figure 7. Note that bit 0 is the first bit of the data word clocked into the shift register. The device has the capability to read out the data word stored in the latch. This is done by parallel loading the data from the latch back into the shift register when the latch signal, LATO, is high. The LATO pulse must occur when SCK is low. Then, the data word can be shifted out of the register
serially to the output, SOD, on falling edges of the shift clock, SCK. The loading and reading of the data word can be done continuously or in bursts. Since the shift register and latch circuitry inside the device is static, there are no minimum frequency requirements on the clocks or data pulses. However, there is some coupling of the digital signals in the analog section. If this coupling is undesirable, the data can be clocked in bursts during non critical intervals, or the data rate can be done at a frequency outside the analog frequency range. The clocks used to shift and latch data (SCK, LATI, LATO) are not related internally to the master clock and can occur asynchronous to CLK.
SCK
0
1
2
3
4
5
6
7
8
9
10
11
12
13
SID
BP
H0
H1
H2
H3
B0
B1
B2
B3
S0
S1
S2
S3
NL/L
LATI
LATO
SOD
a) LOAD
SCK
0
1
2
3
4
5
6
7
8
9
10
11
12
13
SID
LATI
LATO
SOD
BP
H0
H1
H2
H3
B0
B1
B2
B3
S0
S1
S2
S3
NL/L
b) READ
Figure 6. Serial Timing
NL/L NL/L 13 S3 12 SLOPE S2 11 S1 10 S0 9 B3 8 BANDWIDTH B2 7 B1 6 B0 5 H3 4 HEIGHT H2 3 H1 2 H0 1 BYPASS BP 0 FUNCTION BIT NUMBER
Figure 7. 14-Bit Latch
REV. 1.1.1 3/19/01
9
ML2021
PRODUCT SPECIFICATION
Powerdown Mode
A powerdown mode can be selected with pin PDN. When PDN = 1, the device is powered down. In this state, the power consumption is reduced by removing power from the analog section and forcing the analog output, VOUT, to a high impedance state. While the device is in power down mode, the digital section is still functional and the current data word remains stored in the latch. The master clock, CLK, can be left active or removed during powerdown mode. When PDN = 0, the device is in normal operation.
Power Supplies
The digital section inside the device is powered between VCC and GND, or 5 volts. The analog section is powered between VCC and VSS, or 5 volts. The analog section uses AGND as the reference point. GND and AGND are totally isolated inside the device to minimize coupling from the digital section into the analog section. Typically this is less than 100 V. However, ANGD and GND should be tied together physically near the device and close to the common power supply ground connection. The power supply rejection of VCC and VSS to the analog output is greater than -60dB at 1 kHz, typically. If decoupling of the power supplies is still necessary in a system, VCC and VSS should be decoupled with respect to AGND.
Applications
ML2004 LOG GAIN/ATTEN ML2021 EQUALIZER
VIN
VOUT
VIN
VOUT
SCK
SCK
LATI
P
Figure 8. Typical Serial Interface
ML2021 OR ML2004
ML2021 OR ML2004
LATI
SID
SID
ML2021 OR ML2004
VIN SCK LATI SID
VOUT SOD
VIN SCK LATI SID
VOUT SOD
VIN SCK LATI SID
VOUT SOD
P
Figure 9. Controlling Multiple ML2021 and ML2004 With Only 3 Digital Lines Using One Long Data Word
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REV. 1.1.1 3/19/01
ML2021
PRODUCT SPECIFICATION
Ordering Information
Part Number ML2021CP ML2021CS ML2021IP ML2021IS Temperature Range 0C to 70C 0C to 70C -40C to 85C -40C to 85C Package Molded DIP (P16) Molded SOIC (S18) Molded DIP (P16) Molded SOIC (S18)
DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
www.fairchildsemi.com 3/19/01 0.0m 003 Stock#DS300042021 2001 Fairchild Semiconductor Corporation
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

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